ECE 465---Digital Systems

Instructor: Prof. Shantanu Dutt

Important Information:
  1. T/Th 3:30-4:45 pm.

  2. Instructor's office hrs (930 SEO): T/Th 5:00-6 pm.

  3. TA: Teaching Assistants:
    Xiuyan Zhang, Xiuyan Zhang, xzhang87@uic.edu, Office Hrs: Tentatively Tue. & Thu. 2pm - 3pm, in 1333 SEO.

  4. Syllabus: pdf

  5. Lecture Notes

  6. Background Discrete Math Notes

  7. Quartus II Schematic Capture Based Simulation Tool:
    (i) Schematic capture tutorial: pdf
    (ii) Schematic capture plus hierarchical design plus timing simulation tutorial: pdf
    (iii) HDL based design tutorial (not needed): pdf

  8. Instructions for Downloading, Retrieving and Printing Postscript or PDF Files

  9. Very Important:
    (a) Before the next lecture, remember to always go through the material covered in the previous lecture and make sure you understand it all. Ask Qs to TAs and me during office hours, and possibly in the next lecture.
    (b) Also, for background material reading/refreshing specified in the syllabus, always do before the first class of the week specified in which they will be needed.

    This way you'll get the most out of that lecture; otherwise you may not understand much of it, leading to problems in homeworks, projects and exams later on.

Messages:
  1. Sample quiz: pdf

  2. There will be a quiz in week 2 to be submitted on BB. The quiz will cover the following background/prerequisite topics (sections in text where the topics are discussed are given in square brackets):
    1. Boolean Algebra: [2.1-2.2]
    2. K-maps: [3.1-3.7]
    3. Logic gates, synthesis of combinational logic circuits using gates (especially NAND/NOR), word problems for combinational logic circuit synthesis: [2.3-2.4.1, 2.5-2.6]
    4. Fundamental difference between combinational and sequential circuits and which is required for which problem types.