ECE 465---Digital Systems

Instructor: Prof. Shantanu Dutt

Important Information:
  1. T/Th 3:30-4:45 pm.

  2. Instructor's office hrs (930 SEO): T/Th 5:00-6 pm.

  3. TA: Teaching Assistants:
    Xiuyan Zhang, Xiuyan Zhang,, Office Hrs: Tentatively Tue. & Thu. 2pm - 3pm, in 1333 SEO.

  4. Syllabus: pdf

  5. Lecture Notes

  6. Background Discrete Math Notes

  7. Tutorials: Quartus II Schematic Capture Based Simulation Tool and Synopsys's Design Vision Delay, Area and Power Reporting Tool:
    (i) Part I (Setup): pdf
    (ii) Part II (Quartus plus the need for Design Vision): pdf
    (iii) Part III ( Design Vision): pdf
    (iv) Part IV (Debugging): pdf

  8. Instructions for Downloading, Retrieving and Printing Postscript or PDF Files

  9. Very Important:
    (a) Before the next lecture, remember to always go through the material covered in the previous lecture and make sure you understand it all. Ask Qs to TAs and me during office hours, and possibly in the next lecture.
    (b) Also, for background material reading/refreshing specified in the syllabus, always do before the first class of the week specified in which they will be needed.

    This way you'll get the most out of that lecture; otherwise you may not understand much of it, leading to problems in homeworks, projects and exams later on.

  1. (i) Sample Final 1 (pdf) (probs 4, 5 and 6 are not in the current syllabus)
    Sample Final 1 Solutions (pdf)
    (Note: Solution for prob. 2, or a very similar problem, is available for the vorresponding homework).
    (ii) Sample 2 (action FSM) (pdf)

  2. Syllabus for the final:
    (i) Divide-and-Conquer.
    (ii) Computational FSMs, Action/Control FSMs, including D&C for FSM design.
    (iii) Sequential circuit synthesis (classical binary-coded and 1-hot designs)
    (iv) Timing Issues and Clocking Methodologies (minus 2-phase non-verlapping clocking) for synchronous sequential circuits

  3. Midterm Syllabus:
    (i) Basics: TT-based design, K-maps, Boolean algebra, circuit delay determination
    (ii) D&C based digital design and analysis.
    (iii) QM and Petrick's logic minimization techniques.

  4. Sample midterms (only Qs relating to above topics are relevant for the midterm exam):
    (i) Midterm Qs and Solutions (only probs. 1 and 3 correspond to the above syllabus): pdf
    (ii) Midterm Qs (only prob.2 corresponds to the above syllabus, and in it replace the term speculate/speculative by DAC): pdf and Solutions: pdf
    (iii) Sample D&C Problem: pdf

  5. Sample quiz: pdf

  6. There will be a quiz in week 2 to be submitted on BB. The quiz will cover the following background/prerequisite topics (sections in text where the topics are discussed are given in square brackets):
    1. Boolean Algebra: [2.1-2.2]
    2. K-maps: [3.1-3.7]
    3. Logic gates, synthesis of combinational logic circuits using gates (especially NAND/NOR), word problems for combinational logic circuit synthesis: [2.3-2.4.1, 2.5-2.6]
    4. Fundamental difference between combinational and sequential circuits and which is required for which problem types.