ECE 368---CAD Based Logic Design

Instructor: Prof. Shantanu Dutt

Important Information:
  1. M/W/F 2-2:50pm, 219 TH.

  2. Instructor's office hrs (930 SEO): W 5:30-6:30 pm, F 3:30-4:30 pm.

  3. TA: Charles Martin,
    Office Hrs: M W 3-4PM, Office:

  4. Before the next lecture, remember to always go through the material covered in the previous lecture and make sure you understand it all. Ask Qs to TAs and me during office hours, and possibly in the next lecture.

  5. Always do the given reading assignment for the class in which it will be needed. This way you'll get the most out of that lecture; otherwise you may not understand much of it. The reading assignments generally cover background material from pre-requisite courses or some nitty-gritty details like program syntax that are self explanatory.

  6. Syllabus: pdf

  7. A possible VHDL PC software along with an introductory VHDL tutorial: VHDL s/w and tutorial link

  8. Other useful VHDL sources:

    (1) VHDL FAQs, etc.

    (2) On-line resources of the Ashenden textbook

  9. Quartus Schematic Capture Based Simulation Tool: pdf

  10. VHDL Language Reference Manual: Not available at this time

  11. Lecture Notes

  12. Lab instructions for setting up the Synopsys VHDL software and running it (for your lab assignments) (pdf).
    IGNORE html instr as indicated (pdf is more recent version) + Source codes.

  13. X Windows simulation tool (courtesy of Kevin Green)

  14. UNIX Tutorial for Beginners

  15. The Synopsys Design Compiler introductory document prepared by Li Li is here (pdf) .
    The source files used in the example of this document is here (tarred and gzipped file) .
    Restore the above file using commands:
    "gunzip bcd4to7seg.tar.gz"
    "tar -xvf bcd4to7seg.tar"
    NOTE: After the above commands are executed, you will have the source VHDL files in a sub-dir. called "files"; so make sure you do NOT already have such a sub-directory where you have copied the bcd4to7seg.tar.gz file.

  16. The Synopsys Design Vision introductory document prepared by Soumya Banerjee is here (pdf) .
    The VHDL source files used in the two examples of this document are: ck1.vhd and fsm.vhdl

  1. For the 1st lab attendance on Thurs Jan. 16: Get from item 12 above, the instructions for setting up your ECE computer account properly for running Synopsys tools and then for running these tools on a simple example.

  2. Reading Assignment for week 2-3 from the reference text (can do from any logic design text; sections provided for the reference text---Digital Logic Circuit Analysis and Design, V.P. Nelson, et al., Prentice Hall, 1995.):
    1. Chapter 1 of text.
    2. Introduction to logic design: [0.1-0.2] from ref. text.
    3. Number Systems and Codes:} [1.1-1.2] from ref. text.
    4. Logic gates, synthesis of logic circuits using gates: [2.3-2.4.1, 2.5-2.6] from ref. text.