Bio

Contact Information:

UIC Dept. of Electrical & Computer Engineering, 1020 Sciences and Engineering Offices (SEO), 851 South Morgan St.(M/C 154) Chicago, IL 60607.

Office: 1036 SEO

Fax: 312.996.6465

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Ph.D. Computer Science University of California, San Diego, 2008

B.S. Computer Science Peking University, 2001

Reliability

Computer Aided Design (CAD)

Novel computation paradigms in emerging nanoelectronic systems

Defect and fault tolerance for highly unreliable systems

VLSI test

Design for test (DFT) of digital systems

Ph. D. Dissertation Award: Computer Science & Engineering Department, University of California, San Diego (2008)

CAL-IT2 Fellowship: University of California, San Diego (2001)

Guanghua Scholarship: Beijing University (1998)

ECE 267: Computer Organization I

ECE 366: Computer Organization II

ECE 469: Computer System Design

ECE 491: Graduate Seminar for Research and Teaching Methods

ECE 491: Computer Engineering Seminar

ECE 569: Advanced Topics in Processors & Systems

ECE 594: Special Topic: Testing & Reliability of Digital Systems

Journal Publications

  1. Y. Su and W. Rao, “An Integrated Framework Towards Defect-Tolerant Logic Implementation onto Nanocrossbars”, IEEE Transaction on Computer Aided Design, Volume 33, Number 1, pages 64-75, January 2014.
  2. W. Rao, C. Yang,  R. Karri, and A. Orailoglu “Towards Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge”, IEEE Computer, Volume 44, Number 2, pages 46-53, 2011
  3. W. Rao, A. Orailoglu and R. Karri, “Logic Mapping in Crossbar based Nano Architectures”, IEEE Design & Test of Computers,  Volume 26, Numbers 1, pages 68-77,  January 2009
  4. W. Rao, A. Orailoglu and R. Karri, “Towards Nanoelectronics Processor Architectures”, Journal of Electronic Testing: Theory and Applications (JETTA), Special Issue on Test, Defect Tolerance, and Reliability of Nanoscale Devices,  Volume 23, Numbers 2-3, pages 235-254, June 2007

Conference Proceedings

  1. S. Khaleghi, K. Zhao, and W. Rao, “IC Piracy Prevention via Design Withholding and Entanglement”, IEEE Asia South Pacific Design Automation Conference (ASPDAC), pages 821-826, January 2015 (slides)
  2. D. Giri, M. Vacca, G.  Causapruno, W.  Rao, M. Graziano, and M. Zamboni, “A standard cell approach for MagnetoElastic NML circuits“, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), July 2014
  3. S. Khaleghi and W. Rao, “Spare Sharing Network Enhancement for Scalable Systems”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), October, 2013
  4. S. Banerjee, K. Zhao, W. Rao, and M. Zefran, “Decentralized Self-Balancing Systems”, in IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2013
  5. Y. Su and W. Rao, “Defect-Tolerant Logic Hardening for Crossbar-based Nanosystems”, IEEE Design, Automation, and Test in Europe (DATE), pages 1801 – 1806, March, 2013 (slides)
  6. Y. Su and W. Rao, “Defect-Tolerant Logic Implementation onto Nanocrossbars by Exploiting Mapping and Morphing Simultaneously“, IEEE International Conference on Computer Aided Design (ICCAD), November, 2011 (slides)
  7. Y. Su and W. Rao, “On Mismatch Number Distribution of Nanocrossbar Logic Mapping“, IEEE International Conference on Computer Design (ICCD), October, 2010 (slides)
  8. Y. Su and W. Rao, “Yield Modeling and Assessment for Nanocrossbar Systems“, invited paper,  IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August, 2010
  9.  P. Gavlin and W. Rao, “C6: Exploring the Design Space of Nanoelectronics Systems Using a Model of Consumer/Resource Networks“, University Government Industry Micro/nano (UGIM) Symposium, June, 2010
  10. Y. Su and W. Rao, “Runtime-constrained Yield Model in Nanocrossbar Systems“, University Government Industry Micro/nano (UGIM) Symposium,  June, 2010
  11. Y. Su and W. Rao, “Runtime Analysis for Defect-tolerant Logic Mapping on Nanoscale Crossbar Architectures“, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) , pages 75-78, July, 2009
  12. Y. Su and W. Rao, “Defect Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis“, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), pages 322 – 330, October 2009
  13. I. Polian and W. Rao, “Selective Hardening of NanoPLA Circuits”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), pages 263-271, October 2008
  14. W. Rao, A. Orailoglu and K. Marzullo, “Locality Aware Redundancy Allocation in Nanoelectronic Systems,” IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) , pages 56-63, June 2008
  15. W. Rao and A. Orailoglu, “Towards Fault Tolerant Parallel Prefix Adders in Nanoelectronic Systems”, IEEE Design, Automation, and Test in Europe (DATE), pages 360-365, March, 2008
  16. W. Rao, A. Orailoglu and R. Karri, “Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays”, IEEE Dependable Systems and Networks (DSN), pages 216-224, June 2007
  17. W. Rao, A. Orailoglu and R. Karri, “Logic Level Fault Tolerance Approaches Targeting Nanoelectronic PLAs”, IEEE Design, Automation, and Test in Europe (DATE), pages 865-869, April 2007
  18. W. Rao, A. Orailoglu and R. Karri, “Topology Aware Mapping of Logic Functions onto Nanowire-Based Crossbar Architectures”, IEEE/ACM Design Automation Conference (DAC), pages 723-726, July 2006
  19. W. Rao, A. Orailoglu and R. Karri, “Fault Identification in Reconfigurable Carry Lookahead Adder Implementations Targeting Nanoelectronic Fabrics”, IEEE European Test Symposium (ETS), pages 63-68, May 2006
  20. W. Rao, A. Orailoglu and R. Karri, “Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance”, IEEE VLSI Test Symposium (VTS), pages 214-219, April 2006
  21. W. Rao, A. Orailoglu and R. Karri, “Architecture-Level Fault Tolerant Computation in Nanoelectronic Processors”, IEEE International Conference on Computer Design (ICCD), pages 533-542, October 2005
  22. W. Rao, A. Orailoglu and R. Karri, “Fault Tolerant Nanoelectronic Processor Architectures”, IEEE Asia South Pacific Design Automation Conference (ASPDAC), pages 311-316, January 2005
  23. W. Rao, A. Orailoglu and G. Su, “Frugal Linear Network-Based Test Decompression for Drastic Test Cost Reductions”, IEEE International Conference on Computer Aided Design (ICCAD), pages 721-725, November 2004
  24. W. Rao, A. Orailoglu and R. Karri, “Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems”, IEEE International Test Conference (ITC), pages 472-478, October 2004
  25. W. Rao, I. Bayraktaroglu and A. Orailoglu, “Test Application Time and Volume Compression through Seed Overlapping”, IEEE/ACM Design Automation Conference (DAC), pages 732-737, June 2003
  26. W. Rao and A. Orailoglu, “Virtual Compression through Test Vector Stitching for Scan Based Designs”, IEEE Design, Automation, and Test in Europe (DATE), pages 104-109,  March 2003

Book Chapters

  1. W. Rao, A. Orailoglu and R. Karri, “Towards Nanoelectronics Processor Architectures”, Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability,  Springer, pages 339-372, 2007