Bio

Contact Information:

UIC Dept. of Electrical & Computer Engineering, 1020 Sciences and Engineering Offices (SEO), 851 South Morgan St.(M/C 154) Chicago, IL 60607.

Office: 930 SEO

Laboratory Website: Design Automation and Reconfiguration Technology (DART) Lab

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Ph.D. Computer Science and Engineering University of Michigan, Ann Arbor 1990

M.Tech. in Computer Engineering Indian Institute of Technology, Kharagpur, India 1984.

B.E. Electronics and Communication Engineering Maharaja Sayajirao University of Baroda, Baroda India, 1983

VLSI CAD: Physical design, incremental design, physical synthesis, high-level synthesis (ASICs and FPGAs)

Discrete Optimization

FPGA BIST and trusted design

Fault-Tolerant Computing–Systems and Chips

Parallel and Distributed Computing

ECE 368—CAD Based Logic Design (Spring 2014)

ECE/CS 566—Parallel Processing (Spring 2015)

ECE 565—VLSI Design Automation (Fall 2015)

ECE 366—Computer Architecture (Fall 2001)

ECE 465—Digital Systems (Spring 2016)

EECS 265—Intro. Logic Design (Spring 1998)

Lead Guest Editor for the Special Issue on “New Algorithmic Techniques for Complex EDA Problems” in the VLSI Design journal.

Featured speaker (1 of 2) at Int’l Conference on CAD (ICCAD), 2006, for the paper “A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs”.

Best paper award nomination for the paper “Efficient On-Line Testing of FPGAs with Provable Diagnosabilities”, at the Design Automation Conference, June 2004 , a premier conference for VLSI CAD and testing.

Best Paper award for the paper “A probability-based approach to VLSI circuit partitioning”, at the ACM/IEEE Design Automation Conference, Las Vegas, June 1996.

Most influential paper award for the paper “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures” at the Fault Tolerant Comput. Symp., 1995 (for a paper that appeared in FTCS ’88).

Research Initiation Award from NSF for “Efficient Design of Fault-Tolerant Multiprocessors”, 9/92 – 2/96.

Invited article: S. Dutt, F. Rota, F. Trovo and F. Hanchek, “Fault Tolerance in Computer Systems–From Circuits to Algorithms”, invited article, in Electrical Engineering Handbook, Academic Press, 2004.

Invited article: S. Dutt and D. Boley, “Roundoff Errors”, invited article, in Wiley Encyclopedia of Electrical and Electronics Engineering, Vol. 18, 1999, pp. 617-627.

Invited paper: N.R. Mahapatra and S. Dutt, “New anticipatory load balancing strategies for scalable parallel best-first search”, DIMACS workshop on Parallel Processing of Discrete Optimization Problems, April 1994.

Journals/Book Chapters :

  1. S. Dutt and H. Ren, “Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement with White-Space Satisfaction” (pdf) , accepted for publication, IEEE Trans. VLSI Systems , 2008.
  2. S. Dutt and L. Li, “Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures (pdf) , ACM Transaction on Reconfigurable Technology and Systems (TRETS) , Special Issue on Security in Reconfigurable Systems Design, 2, 1, Article 6 (March 2009), 36 pages.
  3. S. Dutt, V. Verma and V. Suthar, “Built-in-Self-Test of FPGAs with Provable Diagnosabilities and High Diagnostic Coverage with Application to On-Line Testing” (pdf) , IEEE Trans. Computer Aided Design of Integrated Circuits , Feb. 2008, pp. 309-326.
  4. N.R. Mahapatra and S. Dutt, “An efficient delay-optimal distributed termination detection algorithm”, Jour. Parallel and Distr. Computing , Oct. 2007, pp. 1047-1066.
  5. S. Dutt, F. Rota, F. Trovo and F. Hanchek, “Fault Tolerance in Computer Systems—From Circuits to Algorithms”, invited article, inElectrical Engineering Handbook , Ed. Wai-Kai Chen, Academic Press, 2004.
  6. Shantanu Dutt, Vinay Verma and Hasan Arslan, “A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs, TODAES 7(4), pp. 664-693 (2002)
  7. S. Dutt and W. Deng, “VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques”, ACM Trans. Design Automation of Electronic Systems (TODAES) , 7(1), pp. 91-121 (2002) See also at NEC Citation Index for a comprehensive citation and citation context (and more) for the conference version of this paper.
  8. S. Dutt and D. Boley, “Roundoff Errors” invited paper in Wiley Encyclopedia of Electrical and Electronics Engineering , Prof. John Webster, ed.
  9. S. Dutt and W. Deng, “Probabilistic Approaches to VLSI Circuit Partitioning”, IEEE Trans. CAD, Vol. 19, No. 5, May 2000, pp. 534-549. ps(gzipped) , or pdf. Tech. Report (ps) (referenced in above paper that contains all the proofs and formulae derivations). A shorter version of this paper appeared in Proc. Design Automation Conference, June, 1996.
  10. F. Hanchek and S. Dutt, “Methodologies for Tolerating Logic and Interconnect Faults in FPGAs”, IEEE Trans. Computers , Special Issue on Dependable Computing, Jan. 1998, pp. 15-33. See also here at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  11. N.R. Mahapatra and S. Dutt, “Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays” submitted to Jour. Parallel and Distr. Computing.—in 2nd round of review. A shorter version of this paper has appeared in Proc. Fault-Tolerant Computing Symp., June 1996.
  12. S. Dutt and N.R. Mahapatra, “Node Covering, Error Correcting Codes and Multiprocessors with High Average Fault Tolerance”, IEEE Trans. Comput. , Oct. 1997.
  13. S. Dutt and N.R. Trinh, “Are There Advantages to High-Dimension Architectures?: Analysis of k-ary n-cubes for the Class of Parallel Divide-and-Conquer Algorithms”, submitted to IEEE Trans. Parallel and Distr. Systems—in 2nd round of review. A shorter version of this paper has appeared in Proc. International Conf. on Supercomputing, May 1996.
  14. N.R. Mahapatra and S. Dutt, “Scalable global and local hashing strategies for duplicate pruning in parallel A* graph search”, to appear inIEEE Trans. Parallel and Distr. Systems. See also here at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  15. S. Dutt and F. Hanchek, “REMOD: A new hardware- and time-efficient methodology for designing fault-tolerant arithmetic circuits”, to appear in IEEE Trans. on VLSI Systems.
  16. S. Dutt and F.T. Assaad, “Mantissa-preserving operations and robust algorithm-based fault tolerance for matrix computations”, IEEE Trans. Comput., Vol. 45, No. 4, April 1996, pp. 408-424.
  17. N.R. Mahapatra and S. Dutt, “New anticipatory load balancing strategies for scalable parallel best-first search”, American Mathematical Society’s DIMACS Series on Discrete Mathematics and Theoretical Computer Science, Vol. 22, 1995, pp. 197-232. See also here at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  18. S. Dutt and N.R. Mahapatra, “Scalable load-balancing strategies for parallel A* algorithms”, Special Issue on Scalability of Parallel Algorithms and Architectures Journal of Parallel and Distr. Computing, Vol. 22, No. 3, Sept. 1994, pp. 488-505. See also here at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  19. S. Dutt and J.P. Hayes, “A local-sparing design methodology for fault-tolerant multiprocessors” to appear in the Special Issue on Graph Theory in Computer Science, Chemistry, and Other Fields of Computers and Mathematics with Applications, Elsevier Science.
  20. S. Dutt and J.P. Hayes, “Some practical issues in the design of fault-tolerant multiprocessors”, IEEE Trans. Comput., Special Issue on Fault-Tolerant Computing, Vol. 41, May 1992, pp. 588-598.
  21. S. Dutt and J.P. Hayes, “Designing fault-tolerant systems using automorphisms”, Journal of Parallel and Distr. Computing, July 1991, pp. 249-268.
  22. S. Dutt and J.P. Hayes, “Subcube allocation in hypercube computers”, IEEE Trans. Comput., Vol. 40, March 1991, pp. 341-352.
  23. S. Dutt and J.P. Hayes, “On designing and reconfiguring k-fault-tolerant tree architectures”, IEEE Trans. Comput., Special Issue on Fault-Tolerant Computing, Vol. 39, April 1990, pp. 490-503.

Refereed Conferences :

  1. Shantanu Dutt, Yang Dai, Huan Ren, and Joel Fontanarosa, “Selection of Multiple SNPs in Case-Control Association Study Using a Discretized Network Flow Approach”, (pdf) , Proc. of BICoB 2009, Springer Lecture Notes in Computer Science , pp. 211-223. Presentations slides: ppt
  2. Huan Ren and Shantanu Dutt, “Algorithms for Simultaneous Consideration of Multiple Physical Synthesis Transforms for Timing Closure”, (pdf) , Proc. Int’l Conf. CAD (ICCAD) , 2008. Presentations slides: ppt
  3. Huan Ren and Shantanu Dutt, “A Network-Flow Based Cell Sizing Algorithm”, (pdf) , Proc. Int’l Workshop on Logic Synthesis (IWLS) ”, pp. 7-14, June 2008.
  4. Huan Ren and Shantanu Dutt, “Constraint Satisfaction in Incremental Placement with Application to Performance Optimization under Power Constraints”, (pdf) , Proc. Int’l Conf. Computer Design (ICCD) 2007 , Oct. 2007.
  5. Shantanu Dutt, Huan Ren, Fenghua Yuan and Vishal Suthar, “A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs”(pdf) , Proc. Int’l Conf. CAD (ICCAD) 2006 , Nov 2006. Presentations slides: ppt
  6. Federico Rota, Shantanu Dutt, Sahithi Krishna, “Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream” (pdf) , Proc. Int’l Symp. of Defect and Fault Tolerance (DFT) , 2006, pp. 507-515.
  7. Vishal Suthar and Shantanu Dutt, “Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions” (pdf) , Proc. VLSI Test Symposium (VTS) 2006 , May 2006. Presentations slides: ppt
  8. Shantanu Dutt and Hasan Arslan, “Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations” (pdf) , Proc. DATE’06 , March 2006. Presentations slides: ppt
  9. Vishal Suthar and Shantanu Dutt, “Efficient On-line Interconnect Testing in FPGAs with Provable Detectability for Multiple Faults” (pdf) , Proc. DATE’06 , March 2006. Presentations slides: ppt
  10. V. Suthar and S. Dutt, “High-Diagnosability Online Built-In Self-Test of FPGAs via Iterative Bootstrapping” (pdf) , Proc. GLSVLSI , April 2005.
  11. H. Arslan and S. Dutt, “A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits” (pdf) , Proc. IEEE Int’l. Conf. on Computer Design , Oct. 2004. Presentations slides: ppt
  12. V. Verma, S. Dutt and V. Suthar, “Efficient On-Line Testing of FPGAs with Provable Diagnosabilities” (pdf) , Proc. IEEE/ACM Design Automation Conference, June 2004. Nominated for a Best-Paper Award Presentations slides: ppt
  13. H. Arslan and S. Dutt, “An Effective Hop-Based Detailed Router for FPGAs for Optimizing Track Usage and Circuit Performance” (pdf), Proc. ACM Int’l Great Lakes Symp. on VLSI, April 2004.
  14. V. Verma and S. Dutt, “Roving Testing Using Built-in-Self-Tester Designs for FPGAs with Effective Diagosability” (poster paper) — ppt, ACM Int’l Symp. on Field Programmable Gate Arrays, Feb. 2004.
  15. H. Arslan and S. Dutt, “ROAD: An Order-Impervious Optimal Detailed Router for FPGAs”(pdf) , Int. Conf. on Computer Design , Oct. 2003. Presentations slides: ppt
  16. F. Trovo, S. Dutt and H. Arslan, “Design and Simulation of an EM-Fault-Tolerant Processor with Micro-Rollback, Control-Flow Checking and ECC”, IEEE APS/URSI International Symposium , (digest of abstracts) — ppt , June 2003.
  17. K. Zhong and S. Dutt, “Algorithms for Simultaneous Satisfaction of Multiple Constraints and Objective Optimization in a Placement Flow with Application to Congestion Control” (pdf) , accepted for publication, Proc. Design Automation Conference , June 2002.
  18. S. Dutt and H. Arslan, “Evaluation of Processor Faults Due to EM Interference—Concepts and Simulation Environment — ppt ”,National Radio Science Meeting , Jan. 2002.
  19. V. Verma and S. Dutt, “A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs” (ps) , Proc. IEEE Int. Conf. Comput.-Aided Design , Nov. 2001.
  20. K. Zhong and S. Dutt, “Effective Partition-Driven Placement with Simultaneous Level Processing and Global Net Views” (ps) or pdf ,Proc. IEEE Int. Conf. Comput.-Aided Design , pp. 254-259, Nov. 2000.
  21. S. Dutt, V. Shanmugavel and S. Trimberger, “Efficient Incremental Rerouting for Fault Reconfiguration in Field Programmable Gate Arrays” ps , Proc. IEEE Int. Conf. Comput.-Aided Design , pp. 173-176, Nov. 1999.
  22. N. R. Mahapatra and S. Dutt, “Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs” ps , Proc. 29th Annual International Symposium on Fault-Tolerant Computing (FTCS-29) , June 1999, pp. 122-129.
  23. S. Dutt and H. Theny, “Partitioning Using Second-Order Information and Stochastic-Gain Functions”, Proc. ACM Int’l Symp. on Physical Design , April 1998. See also here at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  24. N.R. Mahapatra and S. Dutt, “Adaptive Quality Equalizing: High-Performance Load Balancing for Parallel Branch-and-Bound Across Applications and Computing Systems”, Proc. Joint IEEE Parallel Processing Symposium/ Symp. on Parallel and Distr. Processing , April 1998.
  25. S. Dutt, “A Stochastic Approach to Timing-Driven Partitioning and Placement with Accurate Net and Gain Modeling”, TAU97: IEEE/ACM Int. Workshop on Timing Issues in Digital Systems , Dec. 1997, pp. 246-256.
  26. S. Dutt and H. Theny, “Partitioning Around Roadblocks: Tackling Constraints with Intermediate Relaxations”, IEEE/ACM International Conference on CAD , Nov., 1997. See also at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  27. S. Dutt and W. Deng, “VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques”, in Proc. IEEE/ACM International Conference on CAD, Nov. 1996. See also at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  28. F. Hanchek and S. Dutt, “Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs”, Proc. Int. Conf. on Computer Design, Oct. 1996.
  29. N.R. Mahapatra and S. Dutt, “Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Processor Arrays”, Proc. Fault-Tolerant Computing Symp., June 1996, pp. 272-281.
  30. N.R. Mahapatra and S. Dutt, “Sequential and parallel branch-and-bound search under limited-memory constraints”, in Proc. Parallel Optimization Colloquium, Versailles. France, March 1996, pp. 147-166.
  31. S. Dutt and W. Deng, “VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques”, Proc. Physical Design Workshop, April 1996, pp. 92-99. See also here at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  32. S. Dutt and W. Deng, “A probability-based approach to VLSI circuit partitioning”, Proc. Design Automation Conference, June 1996, pp. 100-105; Recepient of Best-Paper Award.
  33. S. Dutt and N.R. Trinh, “Are There Advantages to High-Dimension Architectures?: Analysis of k-ary n-cubes for the Class of Parallel Divide-and-Conquer Algorithms”, Proc. International Conf. on Supercomputing, May 1996, pp. 398-406.
  34. N.R. Mahapatra and S. Dutt, “Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing”,Proc. Tenth IEEE Parallel Processing Symposium, April 1996, pp. 881-885. See also here at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  35. F. Hanchek and S. Dutt, “Node-covering based defect and fault tolerance methods for increased yield in FPGAs”, Proc. International Conference on VLSI Design, Jan. 1996, pp. 225-229.
  36. S. Dutt and N.R. Mahapatra, “Node Covering, Error Correcting Codes and Multiprocessors with High Average Fault Tolerance”, in Proc. Fault-Tolerant Computing Symp., June 1995, pp. 320-329.
  37. N.R. Mahapatra and S. Dutt, “New anticipatory load balancing strategies for scalable parallel best-first search”, DIMACS workshop on Parallel Processing of Discrete Optimization Problems, April 1994; Invited Paper .
  38. S. Dutt, “Fast polylog-time reconfiguration of structurally fault-tolerant multiprocessors”, Proc. Fifth IEEE Symposium on Parallel and Distr. Processing, Dec. 1993, pp. 762-770.
  39. N.R. Mahapatra and S. Dutt, “Scalable duplicate-pruning strategies for parallel A* graph search”, Proc. Fifth IEEE Symposium on Parallel and Distr. Processing, Dec. 1993, pp. 290-297. See also here at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  40. S. Dutt, “New faster Kernighan-Lin-type graph-partitioning algorithms”, Proc. IEEE/ACM International Conference on CAD, Nov. 1993.
  41. S. Dutt and N.R. Mahapatra, “Parallel A* algorithms and their performance on hypercube multiprocessors”, Proc. Seventh IEEE Parallel Processing Symposium, 1993, pp. 797-803. See also here at NEC Citation Index for a comprehensive citation and citation context (and more) for this paper.
  42. F.T. Assaad and S. Dutt, “More robust tests in algorithm-based fault-tolerant matrix multiplication”, The Twenty-Second Fault-Tolerant Computing Symp., July 1992, Boston, pp. 430-439.
  43. S. Dutt and J.P. Hayes, “Some practical issues in the design of fault-tolerant multiprocessors”, Proc. Twenty-First Fault Tolerant Computing Symp., June 1991, Montreal, Canada, pp. 292-299.
  44. S. Dutt and J.P. Hayes, “An automorphic approach to the design of fault-tolerant multiprocessors”, Proc. Nineteenth Fault Tolerant Comput. Symp., June 1989, Chicago, pp. 496-503.
  45. S. Dutt and J.P. Hayes, “On designing fault-tolerant multiprocessor systems”, International Workshop on Hardware Fault Tolerance in Multiprocessors, June 1989, Urbana-Champaign, pp. 48-51.
  46. S. Dutt and J.P. Hayes, “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures”, Proc. Eighteenth Fault Tolerant Comput. Symp., June 1988, Tokyo, pp. 328-333; Judged as one of the most influential papers published in the first 25 years of FTCS (1971-1995). Has reappeared in a Special Silver Jubilee Issue of FTCS published by IEEE Computer Soc. Press.
  47. S. Dutt and J.P. Hayes, “On allocating subcubes in a hypercube multiprocessor”, Proc. Third Conf. on Hypercube Computers, Jan. 1988, pp. 801-810.