Bio

Contact Information:

UIC Dept. of Electrical & Computer Engineering, 1020 Sciences and Engineering Offices (SEO), 851 South Morgan St.(M/C 154) Chicago, IL 60607.

Ph.D Computer Science
University of Illinois at Urbana-Champaign, 1986

M.S. Computer Science
Korea Adavnced Institute of Science and Technology, 1979

B.S. Mathematics
Sogang University, 1977

Associate Editor, IEEE Transactions on Parallel and Distributed Computing

Subject area editor, Journal of Parallel and Distributed Computing

Editorial Board, Parallel Computing

Program committee chair, the 6th IEEE Workshop on Interaction between Compilers and Computer Architectures, Feb. 2002

Self-invalidation method for reducing coherence overheads in a bus-based shared-memory multiprocessor apparatus, U.S. Patent No. 5,835,950, Nov. 1998 (with S. Cho)

Distinguished visitor, IEEE Computer Society (2000 – 2002)

Non-Inclusive Memory Access Mechanism, U.S. Patent No. 5,937,431, Aug. 1999 (with J.Kong)

Block Replacement Method in Cache Only Memory Architecture Multiprocessor, U.S. Patent No.5,692,149, Nov. 1997.

Best Paper Award, the 12th IEEE Int’l Conf. Computer Communications and Networks, Dallas, Texas, Oct. 2003

Outstanding Paper Award, the 15th IEEE International Conference on Parallel Processing, Aug. 1986.

Computer architecture

Microprocessor and networking hardware design

Compiler optimization

Computer system security