Bio

Contact Information:

UIC Dept. of Electrical & Computer Engineering, 1020 Sciences and Engineering Offices (SEO), 851 South Morgan St.(M/C 154) Chicago, IL 60607.

Office: 3015 ERF

Lab Website: Advanced Electronics of Nano- Devices (AEON) Lab

PhD, Georgia Institute of Technology, Atlanta 2010-2015

B. Tech., Indian Institute of Technology, Kanpur 2003-2007

M. Tech., Indian Institute of Technology, Kanpur 2007-2008

Ultralow power circuits and systems

Circuit design with emerging technologies

Hardware security

Neuromorphic computing

Oscillatory and chaotic computing

Sigma-Xi Best PhD Dissertation in 2015. []

IEEE Electron Device Society (EDS) Fellowship (one of the three recipients worldwide) in 2014. [read]

Authored Most Downloaded Journal in IEEE Transactions of Nanotechnology in 2014.

Academic Excellence Award from Indian Institute of Technology, Kanpur in 2005.

Journals

  1. Mohammad Faisal Amir, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “Exploration of Si/Ge Tunnel FET Bit Cells for Ultra-low Power Embedded Memory,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems , 2016.
  2. Denny Lie, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “Impact of Heterogeneous Technology Integration on the Power, Performance, and Quality of a 3D Image Sensor,” IEEE Transactions on Multi-Scale Computing Systems , 2016.
  3. Amit Ranjan Trivedi, Khondker Ahmed, and Saibal Mukhopadhyay, “Negative Gate Transconductance in Gate/Source Overlapped Heterojunction Tunnel FET and application to Single Transistor Phase Encoder,” IEEE Electron Device Letters , 2015. [read]
  4. Amit Ranjan Trivedi, Suman Datta, and Saibal Mukhopadhyay, “Application of Silicon-Germanium Source Tunnel-FET to Enable Ultralow Power Cellular Neural Network-Based Associative Memory,” IEEE Transaction of Electron Devices , vol. 61, no. 11, Nov. 2014. [read]
  5. Amit Ranjan Trivedi, Amith Singhee, Pranita Kerber, Takashi Ando, David Frank, and Saibal Mukhopadhyay, “A Simulation study of Oxygen vacancy induced variability in high-k/metal-gate SOI FinFET,” IEEE Transaction of Electron Devices , vol. 61, no. 5, May 2014.[read]
  6. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Potential of SiGe Tunneling Nanowires for Ultra-low Power Image Processing,” IEEE Transaction of Nanotechnology , vol. 31, no. 4, July 2014. [read]
  7. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “In-situ Power Gating Efficiency Learner for Self Adaptive Power Gating,” IEEE Transaction of Circuits and Systems II , vol. 61, no. 5, May 2014. [read]
  8. Wen Yueh, Subho Chatterjee, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “Performance and Robustness of 3D integrated SRAM Considering Tier-to-tier Thermal and Supply Cross-talk,” IEEE Transactions on Components, Packaging and Manufacturing Technology , vol. 3, no. 6, June 2013.[read]
  9. Tarun Kumar Agarwal, Amit Ranjan Trivedi, Vaidyanathan Subramanian, and M. Jagadesh Kumar, “Compact Modeling of Partially Depleted Silicon-on-Insulator Drain-Extended MOSFET (DEMOS) including High-voltage and Floating Body Effects,” IEEE Transaction of Electron Devices , vol. 58, no. 10, Oct 2011. [read]
  10. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Through-Oxide-Via-Induced Back-Gate Effect in 3-D Integrated FDSOI Devices,” IEEE Electron Device Letters , vol. 32, no. 8, 2011. [read]
  11. Amit Ranjan Trivedi and Supriyo Bandyopadhyay, “Single spin Toffoli-Fredkin logic gate,” Journals of Applied Physics , vol. 103, no. 10, May 2008. [read]
  12. Amit Ranjan Trivedi, Supriyo Bandyopadhyay, and M. Cahay, “Switching Voltage, Dynamic power Dissipation and on-to-off conductance ratio of a spin field effect transistor” IET Circuits, Devices & Systems , vol. 1, no. 6, Dec. 2007. [read]

Conferences

  1. Amit Ranjan Trivedi, Suman Datta, and Saibal Mukhopadhyay “Ultralow Power Neuromorphic Associative Processing with Si/Ge and InAs/GaSb Heterojunction TFET,” GOMACTech conference , 2016.
  2. Susmita Dey Manasi and Amit Ranjan Trivedi, “Gate/Source-Overlapped Heterojunction Tunnel FET-based LAMSTAR Neural Network and its Application to EEG Signal Classification,” IEEE Joint Conference on Neural Networks (IJCNN) , 2016.
  3. Amit Ranjan Trivedi, Rahul Pandey, Huichu Liu, Suman Datta, and Saibal Mukhopadhyay. “Gate/Source overlapped heterojunction tunnel FET for non-Boolean associative processing with plasticity,” IEEE International Electron Devices Meeting (IEDM), 2015. [read]
  4. Sravan Marella, Amit Ranjan Trivedi, Saibal Mukhopadhyay, and Sachin S. Sapatnekar. “Optimization of FinFET-based circuits using a dual gate pitch technique,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015. [read]
  5. Mohammad Faisal Amir, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “A Tunnel-FET SRAM Array for Energy-Efficient Embedded Memory Blocks in Reconfigurable Computing Platforms,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference , 2014. [read]
  6. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Si/Ge Tunneling Nanowires based Low Power Cellular Neural Network,” GOMACTech conference , 2014.
  7. Amit Ranjan Trivedi, Mohammad Faisal Amir, and Saibal Mukhopadhyay, “Ultralow Power Electronics with Si/Ge Tunnel FET,” IEEE Design Automation and Test in Europe , 2014. [read]
  8. Krishnamurthy Yeleswarapu, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “Simulation of the TSV-to-Device Coupling in 3D ICs for Short Channel Strained Silicon Transistors,” IEEE Electrical Performance of Electronic Packaging and Systems , 2013. [read]
  9. Amit Ranjan Trivedi, Sergio Carlo, and Saibal Mukhopadhyay, “Exploring Tunnel-FET for ultra-low power analog applications: A case study for Operational Transconductance Amplifier,” ACM Design Automation Conference , 2013. [read]
  10. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Self Adaptive Power-Gating Scheme by On-Line Characterization of Energy Inflection Activity,” SRC TECHCON , 2012.
  11. Amit Ranjan Trivedi and Saibal Mukhopadhyay, “Self-Adaptive Power Gating with Test Circuit for On-line Characterization of Energy Inflection Activity,” IEEE VLSI Test Symposium , 2012.
  12. Wen Yueh, Subho Chatterjee, Amit Ranjan Trivedi, and Saibal Mukhopadhyay, “On the Parameteric Failures of SRAM in a 3D-die Stack considering Tier-to-Tier Supply Cross-talk,” IEEE VLSI Test Symposium , 2012. [read]
  13. S. Parthasarathy, Amit Ranjan Trivedi, S. Sirohi, R. Groves, M. Olsen, Y. S. Chauhan, M. Carroll, D. Kerr, A. Tombak, P. Mason, “RF SOI Switch FET Design and Modeling Trade-offs for GSM Applications,” IEEE International Conference on VLSI Design , 2010. [read]

Disclosures

  1. Amit Ranjan Trivedi, Jaydeep Kulkarni, Muhammad Khellah, Carlos Tokunaga, Dinesh Somasekhar, and James Tschanz, “Area efficient, high speed, physical-design friendly, small supply differential, current steering level shifter,” 2014. (pending, filed through Intel corporation)
  2. Amit Ranjan Trivedi, Jaydeep Kulkarni, Muhammad Khellah, Carlos Tokunaga, and James Tschanz, “Delta VDD aware VMIN assist techniques for ultra-low voltage level shifter,” 2014. (pending, filed through Intel corporation)