Current Research Projects:

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Compound Noise Analysis	Traditional noise analysis attempts to model noise sources one at a time, and allocates maximum individual budget, which sometimes results in over or under design, since it ignores the fact that multiple noise sources on a circuit path may combine with each other, greatly increasing or decreasing the possibility of having an error. Therefore, analysis of the impacts of multiple simultaneously active noise sources, which can be defined as compound noise analysis will be necessary to overcome the limitations of stand alone noise analysis. Again, since noise induced deviation at an evaluation node will reflect the cumulative effect of multiple active sources, it is important to separate the contaminating noise sources, and estimate relative contributions of these sources in the observed noise to determine what types of remedial steps can be taken. There have been very few works published on these issues, which includes some of the PI’s recent works. The growing dominance of signal integrity problems and the evolving reality of multiple noise sources interacting with each other are pressing the need for the development of algorithms/techniques to study the cumulative noise effects, and analyze individual and relative contributions of different noise sources when a compound noise measurement
Interconnect Pipelining	With technology scaling various optimization techniques, such as, aggressive repeater insertion (nearly 10^6 repeaters required for 50nm compared to about 10^4 in 180nm processors), optimization of line dimensions, advancement of interconnect materials (copper from 180-nm generations), and use of low dielectric constant materials (3.55 in 250-nm and 1.5 in 70-nm technology) are not sufficient to provide the ultimate solution to the increasing performance mismatches between device and interconnects. The incompatibility between interconnect needs at the projected cross-chip clock rates and achievable performance will become worse in future. Interconnect delays far exceed the device delays, and multiple clock cycles may be needed for signals to travel over global networks. Aggressive repeater insertion in nanometer circuit makes power management very difficult, since the resulting power density can exceed 100 W/cm^2. Hence, new material innovation, accelerated design techniques, and unconventional methodologies are required to overcome the limitations of today’s copper and low-к metallization and repeater insertion based interconnect systems. To support multi-cycle signal communication a feasible solution is to insert sequential elements in interconnects lines – a concept that has become known as interconnect pipelining. The idea is to divide a wire, whose delay is longer than one clock cycle, into several segments by inserting sequential elements to store signal values that require multiple clock cycles to travel through a particular global wire. It is important to explore the prospects and penalties of this new concept in terms of speed, area, power and overall performance gain; and identify possible challenges to implement this new technique. A comparative analysis of the advantages and disadvantages of different options of interconnect pipelining is necessary. Analytical models and algorithms must be developed for the estimation of the required resources, and also for design automation. These models and algorithms must be able to handle the impacts of technology scaling, process and parametric variations, and non ideal behaviors of signals and circuits.
Package-Chip Co-Design	21^st century electronic market is driven by consumers’ demands for technologies to provide immediate access to entertainment, information and communication system anywhere at anytime in a personalized fashion and at an affordable price. It requires shorter product cycles, higher level of integration, higher speed, and low-power consumption. To cope with this trend System-In-Package (SIP) and System-On-Package (SOP) technologies will take a significant portion of existing ULSI technology to extend the level of integration. However, the demand for very high performance System-on-Chip (SOC) will also remain very high. As a result, the required package is increasingly complicated in terms of number of pins, frequency response, signal integrity, electrical reliability and thermo-mechanical stability. The tolerable margins of both the chip and the package level design have become more stringent, and many of the issues concerning the die also concern the package. Indeed, the interface and the interaction between the die and the package has become a new area of focus due to the impact of the package on the total die/package sub-system performance as well as electro-mechanical integrity and the need to reflect this impact in the package design. Consequently, stand-alone approaches of chip and package design will be inadequate, and design and analysis methodologies and tools must consider the co-design features. By eliminating unduly specialized work on either chip or package in isolation in favor of approaches that optimize the chip-package sub-system as a whole, redundant effort can be minimized and overall performance can be optimized by realizing package-chip co-design. Therefore, it is important to identify design problems (i.e. global signals/ signal integrity, clock distribution) that can be and need to be addressed simultaneously at the chip and package levels
Inductance in Performance and Reliability Analysis	So far, most of the research in signal integrity, power and timing analysis is based on RC models including capacitive coupling. Circuit designers have proposed various figures of merit (FOMs) based these RC models, which assume that the total inductance is less than a critical inductance, and the system is over damped. However, due to increasing frequencies, faster signal transition times, introduction of low resistive copper interconnect, and new dielectrics to reduce interconnect capacitance, inductance and inductive coupling become prominent for some signal lines in the multilayer interconnects networks at the chip and package levels, which will change the methodology of circuit optimization, and the way different FOMs are defined. It has been illustrated that inductance can be exploited to improve some aspects of high speed integrated circuits performance. On the other hand, voltage overshoots due to inductance and inductive coupling will lead to delay variation, which is very difficult to estimate due to lack of accurate models and figures of merit including inductance. The voltage overshoot may lead to very high effective gate voltage stress, which is a serious concern for gate oxide reliability in current ultra-thin (1-5 nm) MOS gate dielectrics, since failure rate is exponentially dependent on the effective voltage stress. This issue has not been analyzed in any previous work. Therefore, it is imperative to conduct an in-depth analysis of the positive and negative impacts of on-chip and on-package inductance, and develop RLC model based figures of merit (FOMs) to estimate these impacts.