ECE 567: Advanced VLSI Design 

Credit Hours

4 for Graduate Students

Course Goal

The course will focus on issues that arise in the design, analysis and testing of high speed and high performance VLSI circuits and systems. The course will be based largely on the papers published in reputed journals and conference proceedings with the aim to help students acquire the basic skills for graduate study, collecting and surveying technical materials, initiate ideas for own design project, writing papers, and presentation skills.

Prerequisite

ECE 467: Introduction to VLSI Design

Grading

Paper or Project: 50%             Class Participation: 10%                  Quiz & Exams: 40%

Instructor

Prof. Masud H. Chowdhury

Electrical and Computer Engineering (Room # SEO 923)

Email: masud@ece.uic.edu URL: www.ece.uic.edu/~masud  Phone: 312-996-6016

Major Topics

§         The following topics will be covered in instructor’s lecture and students’ presentation

§         Students are allowed to suggest additional topics related to the scopes of the course

 

 

  1. Review Of MOSFET Devices And Circuit Concepts
    1. Velocity Saturation And Short Channel Effects
    2. Alpha-Power Law Model Of Device Currents
    3. Characteristics Of Static And Dynamic Combinational And Sequential Circuits
  2. Scaling And Interconnect Issues
    1. Technology Scaling And Alternatives
    2. Effects Of R And C On Performance; And Modeling Of  RC Lines
    3. Skin And Proximity Effects
    4. Electromigration And Interconnect Reliability
    5. Interconnect Delay Modeling, Elmore Delay And Wyatt’s Approximation
    6. Repeater Insertion In RC Line To Improve Delay
    7. Inductive Effects In High Speed Integrated Circuits
    8. Frequency Dependent Interconnect In Integrated Circuits
    9. Extraction And Estimation Of Interconnect Elements (R, L, C)
    10. Advanced Interconnect Techniques
  3. Advanced Techniques For Integrated Circuits Design
    1. Dual Rail Logic Circuits
    2. CMOS Output Stage; And Buffers To Drive Large Capacitive Load
    3. BiCMOS Circuits
    4. Tri-State Circuits
    5. Silicon Over Insulator (SOI) Devices And Circuits
  4. Simulation, Analysis And Modeling Of Deep Submicron Integrated Circuits
    1. Moment Matching Techniques For Interconnect Simulation
    2. Model Order Reduction
    3. Realizable Reduction Of Integrated Circuits
  5. Noise And Signal Integrity Issues
    1. Sources And Types Of Noise In Integrated Circuits
    2. Effects Of Noise On Static And Dynamic Circuits
    3. Evaluation Of Noise Pulse And Amplitude In Coupled RC And RLC Lines
    4. Analysis Of Coupling Noise In Static And Dynamic Circuits
    5. Leakage And Substrate Noise Problems In Digital Integrated Circuits
  6. Temperature And Low Power Design Considerations
    1. Adiabatic Circuits
    2. Innovative Power Distribution Scheme And Related Issues
    3. Effects Of IR Drop And Ldi/Dt Noise In The Power Distribution Network
    4. Simultaneously Switching Noise (SSN)
    5. High Temperature Effects In Integrated Circuits
  7. Timing Analysis And Clocking Challenges At GHz Level
    1. Synchronous Versus Asynchronous Circuits
    2. Innovative Clock Distribution Schemes and Related Issues
    3. Clock Scheduling, Non-Zero Clock Scheduling, And Racing Conditions
    4. Static Timing Of Integrated Circuits
  8. System Level And Physical Design Issues
    1. Timing Driven Placement And Routing
    2. Common And Advanced Placement And Routing Techniques
    3. Circuit Partitioning Techniques
    4. Input And Output Circuits
  9. Transition From Deep Submicron To Nanometer Regime
    1. Nanotechnologies And Nanofabrication
  10. Challenges And Trade-Offs Of System-On-A-Chip (SOC) Design
    1. SOC Solutions For Nanometer Design
    2. Signal Integrity Issues In SOC Environment
  11. FPGA-Based System Design
    1. Low-Power Issues For FPGA
  12. Advanced Memory Issues
  13. VLSI For Wireless Communication
  14. Manufacturability, Reliability And Testing Of VLSI Circuits And Systems