ECE 467: Introduction to VLSI Design
Semester Plan
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Instructor,
TA and Contact Information |
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Instructor |
Prof. Masud H. Chowdhury Room # SEO 923 Electrical and
Computer Engineering Email: masud@ece.uic.edu
URL: www.ece.uic.edu/~masud Phone: 312-996-6016 |
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Office Hours |
Thursday: 3-30 p.m. 5-30 p.m. in SE0 923 or can be reached by email: masud@ece.uic.edu |
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Teaching
Assistant |
Amit
Raichura <araich2@uic.edu> TA
Hours: Tuesday, |
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Class Schedule |
Lecture Class: Tuesday and Thursday: 0200 p.m.-0315 p.m. in 118 DH Lab Class: Tuesday:
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Lecture,
Homework & Exam Schedule |
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Day |
Topics |
Homework* |
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1.
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Lecture 1: Basic Concepts and Issues of Integrated Circuits |
HW-1 (3%) |
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2.
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Lecture 2: Semiconductor Properties and pn
Junction Diode |
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3.
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Lecture 2: Semiconductor Properties and pn
Junction Diode |
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4.
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Lecture 3: Properties of MOSFET (Metal Oxide Field Effect
Transistor) |
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5.
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Lecture 3: Properties of MOSFET (Metal Oxide Field Effect
Transistor) |
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6.
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Lecture 4:Physical Structure and Fabrication Process of
Integrated Circuits |
HW-2 (3%) |
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7.
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Lecture 5:
Introduction to Circuit Simulation and Layout Tools |
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8.
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Lecture 6: The Static CMOS Inverter |
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9.
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Lecture 6: The Static CMOS Inverter |
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10.
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Lecture 7: Different Types of Inverter |
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11.
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Lecture 7: Different Types of Inverter |
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12.
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Exam-1:
Based on Lecture 1-7 (15%) |
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13.
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Lecture 8: Static Combinational Logic Designs |
HW-3 (3%) |
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14.
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Lecture 8: Static Combinational Logic Designs |
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15.
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Lecture 9: Dynamic
Combinational Logic Designs
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16.
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Lecture 9: Dynamic
Combinational Logic Designs
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17.
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Lecture 10: Static Sequential Circuits
Design |
HW-4 (3%) |
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18.
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Lecture 10: Static Sequential Circuits Design |
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19.
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Lecture 11: Dynamic and Other Sequential Circuit Styles |
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20.
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Lecture 11: Dynamic and Other Sequential Circuit Styles |
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21.
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Lecture 12: Designing Arithmetic Circuits in CMOS VLSI |
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22.
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Lecture 12: Designing Arithmetic Circuits in CMOS VLSI |
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23.
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Exam-2:
Based on Lecture 8-12 (20%) |
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24.
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Lecture 13:
Semiconductor Memories
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HW-5 (3%) |
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25.
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Lecture 13:
Semiconductor Memories
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26.
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Lecture 14: Timing
Issues in VLSI Circuits
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27.
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Lecture 15: High Performance Issues - Interconnect and Scaling Issues |
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28.
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Lecture 16: High Performance Issues: Noise and Low Power Design Issues |
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29.
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Lecture 17: Integrated Circuits Implementation Strategies |
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30.
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Lecture 18: System Level and Physical Design Issues |
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31.
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Exam-3:
Problems from Lecture 13-18 + Basic concepts from Lecture 1-12 (25%) |
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* Class Test: Undeclared class test
may be taken in place of homework (1 class test = 1 HW)
Lab & Project
Schedule
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Lab |
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Date |
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1 |
Cadence Lab 1 |
Week-2 |
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2 |
Cadence Lab 1 |
Week-3 |
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3 |
Cadence Lab 1 |
Week-4 |
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4 |
Cadence Lab 1 |
Week-5 |
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Project-1 |
Design, Layout, Extraction and Simulation of a Combinational
Circuit |
Week-10 |
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Project-2 |
Design, Layout, Extraction and Simulation of a Sequential
Circuit |
Final Week |