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Assistant
Professor
Department of Electrical and Computer
Engineering
University of Illinois
at Chicago
Education:
Ph.D from
Polytechnic University, Brooklyn, USA, 2004
Master from University of Science and Technology of China, Hefei, China, 1999
Bachelor from Xidian University, Xi’an, China, 1996
Research
Interests:
Computer
Aided Design (CAD) of fault tolerant VLSI Systems
Countermeasures for side-channel cryptanalysis for crypto devices
Hardware acceleration of secure communications
Robust Nano-Scale Architecture
Services:
Publication Chair of Nanoarch 2005
Reviewer
for IEEE Transactions on Computer
Reviewer
for IEEE Transactions on VLSI
Reviewer for Design Automation and Test in Europe Conference
Reviewer for IEEE International Symposium on Defect and Fault Tolerance in
VLSI Systems
Contact Information:
Office:
1037
SEO
Voice: (312)
413-7573
Fax: (312) 996-6465
Mailing: 1020 SEO (MC 154)
851
S Morgan St
Chicago, IL, 60607
Email: kaijie@ece.uic.edu
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