ECE 565---VLSI Design Automation -- Lecture Notes

Instructor: Prof. Shantanu Dutt

1. Intro. Lecture Notes # 1 ps
   pdf
   
   
2. Intro. Lecture Notes # 2 -- VLSI Design Flow (hardcopy)
   
   
3. Lecture Notes # 3 -- High Level Synthesis (hardcopy)
   
   
4. Lecture Notes # 3b -- High Level Synthesis (courtesy of and copyrighted by Prof. Kia Bazargan) ppt
   
   
5. Lecture Notes # 3c -- Register Allocation in High Level Synthesis pdf
   
   
6. Lecture Notes # 4 -- Chip Layout Styles (hardcopy)
   
   
7. Lecture Notes # 5 -- VLSI Circuit Issues (no notes, actually :-(. But was done in class).
   
   
8. Lecture Notes # 6 -- Partitioning (probability based) ps
   pdf
   
   
9. PROP Papers:
   Conference version: S. Dutt and W. Deng, ``A probability-based approach to VLSI circuit partitioning'', Proc. Design Automation Conference, June 1996, pp. 100-105.
   
   Journal version: S. Dutt and W. Deng, ``Probabilistic Approaches to VLSI Circuit Partitioning'', IEEE Trans. CAD, Vol. 19, No. 5, May 2000, pp. 534-549. ps(gzipped) , or pdf , or
   Print version only for teaching purpose: pdf
   
   
10. Lecture Notes # 7 -- Multilevel Partitioning - Hmetis ppt
    
    
11. Lecture Notes # 8 -- Algorithmic Techniques in VLSI CAD ppt
    
    
12. Floorplanning intro, simulated annealing and mixed integer programming formulation (from Prof. Hai Zhou's web site at NWU) pdf
    
    
13. Yet another (good) FP slide set pdf
    
    
14. Sequence-pair based floorplanning technique: (courtesy of Karthik Chandramouli) pdf
    
    
15. Intro to placement and basic PDP approach and rationale (hard copy)
    
    
16. Quadratic Placement: quadratic and linear WL objectives ppt , pdf
    
    
17. Classical placement algorithms (min-cut, simulated annealing) pdf
    
    
18. Simultaneous level partitioning based PDP: ppt
    
    
19. General and Channel Routing: ppt
    
    
20. Maze and Line Routing: pdf
    
    
21. Global Routing: pdf