ECE 465---Digital Systems
Instructor: Prof. Shantanu Dutt
Messages:
- The final is on Thurs May 5, 3:30 - 5:30 pm in LC C3.
- Proof Example for State Equivalency: pdf
- HW 4 Solutions: pdf
- HW 3 Solutions: CLA soln (pdf)
Rest of the solns (pdf)
- Syllabus for the final:
(i) Divide-&-Conquer design approach
(ii) PLA/PAL based logic design
(iii) Arithmetic Circuits -- Adders & Subtractors
(iv) FSMs, Sequential Circuits and their Synthesis (including 1-hot designs)
(v) State Minimization of Completely and Incompletely specified machines
(vi) Timing Issues
and Clocking Methodologies for Synchronous Seq. Ckts.
- Sample Final 1 (pdf) and
Sample Final 1 Solutions (pdf)
NOTE: Testing is not there in the current finals syllabus.
- Sample Final 2 (pdf)
Solution to Prob. 2 (Equivalency Proof) (txt)
NOTE: Testing is not there in the current finals syllabus.
- HW 4 (due 04/28): pdf
and here is the vending machine fsm solution
of HW 3 (pdf) that you'll need.
- HW 3 (due 04/19): pdf
- Midterm Solutions: pdf
and the Midterm Qs: pdf
- Rest of HW 2 Solutions: pdf
- HW 2 -- Shifter solution: pdf
- Project 2 (due Tue 04/12 -- firm; there will be no postponement.):
pdf
- Syllabus for midterm:
K-maps, QM, multi-function QM, Petrick's algorithm, design of Decoders
(including D&C approach), design of MUxes (including D&C approach),
logic design using MUXes and PLAs/PALs.
- Sample midterm (only in the sense that I gave this midterm
before; your midterm may or may nor resemble this one).
IMPORTANT: Ignore the heuristics for MF-QM given in this midterm;
use the heuristics discussed in class which are somewhat different: pdf
- HW 1 solutions: gzipped pdf
- HW 2 (due 03/10): pdf
- Project 1 (due 03/01---changed to 03/03):
pdf
- Quiz 1 solutions: gzipped pdf
- HW1 (due 02/17): pdf
- Sample quiz (this is a quiz I used last time I taught this course):
pdf
- There will be a quiz on Tue. Feb. 1 that will cover the following
background/prerequisite topics (sections in text where the topics are
discussed are given in square brackets):
- Boolean Algebra: [2.1-2.2]
- K-maps: [3.1-3.7]
- Logic gates, synthesis of logic circuits using gates: [2.3-2.4.1,
2.5-2.6]
- Instructor's office hrs (930 SEO): Tue/Th/Fri 2-3pm.
- TA:
Waseem Ahmad, Office: 1011 SEO, phone: , e-mail: wahmad1@uic.edu, wahmad@acm.org
Office Hrs: T/Th 12-2pm.
- Before the next lecture, remember to always go through the
material covered in the previous lecture and make sure you understand
it all. Ask Qs to TAs and me during office hours, and possibly in the
next lecture.
- Syllabus: pdf
- Lecture Notes
(for some lectures only---not exhaustive)
Instructions for
Downloading, Retrieving and Printing Postscript or PDF Files