ECE 465---Digital Systems

Instructor: Prof. Shantanu Dutt

Messages:
  1. The final is on Thurs May 5, 3:30 - 5:30 pm in LC C3.

  2. Proof Example for State Equivalency: pdf

  3. HW 4 Solutions: pdf

  4. HW 3 Solutions: CLA soln (pdf)
    Rest of the solns (pdf)

  5. Syllabus for the final:
    (i) Divide-&-Conquer design approach
    (ii) PLA/PAL based logic design
    (iii) Arithmetic Circuits -- Adders & Subtractors
    (iv) FSMs, Sequential Circuits and their Synthesis (including 1-hot designs)
    (v) State Minimization of Completely and Incompletely specified machines
    (vi) Timing Issues and Clocking Methodologies for Synchronous Seq. Ckts.

  6. Sample Final 1 (pdf) and
    Sample Final 1 Solutions (pdf)
    NOTE: Testing is not there in the current finals syllabus.

  7. Sample Final 2 (pdf)
    Solution to Prob. 2 (Equivalency Proof) (txt)
    NOTE: Testing is not there in the current finals syllabus.

  8. HW 4 (due 04/28): pdf
    and here is the vending machine fsm solution of HW 3 (pdf) that you'll need.

  9. HW 3 (due 04/19): pdf

  10. Midterm Solutions: pdf
    and the Midterm Qs: pdf

  11. Rest of HW 2 Solutions: pdf

  12. HW 2 -- Shifter solution: pdf

  13. Project 2 (due Tue 04/12 -- firm; there will be no postponement.): pdf

  14. Syllabus for midterm: K-maps, QM, multi-function QM, Petrick's algorithm, design of Decoders (including D&C approach), design of MUxes (including D&C approach), logic design using MUXes and PLAs/PALs.

  15. Sample midterm (only in the sense that I gave this midterm before; your midterm may or may nor resemble this one).
    IMPORTANT: Ignore the heuristics for MF-QM given in this midterm; use the heuristics discussed in class which are somewhat different: pdf

  16. HW 1 solutions: gzipped pdf

  17. HW 2 (due 03/10): pdf

  18. Project 1 (due 03/01---changed to 03/03): pdf

  19. Quiz 1 solutions: gzipped pdf

  20. HW1 (due 02/17): pdf

  21. Sample quiz (this is a quiz I used last time I taught this course): pdf

  22. There will be a quiz on Tue. Feb. 1 that will cover the following background/prerequisite topics (sections in text where the topics are discussed are given in square brackets):
    1. Boolean Algebra: [2.1-2.2]
    2. K-maps: [3.1-3.7]
    3. Logic gates, synthesis of logic circuits using gates: [2.3-2.4.1, 2.5-2.6]

  23. Instructor's office hrs (930 SEO): Tue/Th/Fri 2-3pm.

  24. TA:
    Waseem Ahmad, Office: 1011 SEO, phone: , e-mail: wahmad1@uic.edu, wahmad@acm.org
    Office Hrs: T/Th 12-2pm.

  25. Before the next lecture, remember to always go through the material covered in the previous lecture and make sure you understand it all. Ask Qs to TAs and me during office hours, and possibly in the next lecture.

  26. Syllabus: pdf

  27. Lecture Notes (for some lectures only---not exhaustive)

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