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-- Test bench, Lab 3 -- 16 - bit Ripple Carry Adder
-- ECE 368, Instructor: Prof. Shantanu Dutt 
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Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;

use work.rnd2.all;

entity tb is
end entity tb;

architecture str of tb is

component rca is
   port(a, b:in std_logic_vector(15 downto 0);       -- 16 bit i/p's
   		cin: in std_logic;							 -- carry in
        sum:out std_logic_vector(15 downto 0);		 -- sum o/p
		cout: out std_logic);						 -- carry out
end component;

 constant number: natural:=8;
 signal inp1, inp2:std_logic_vector(15 downto 0) := (others => '0');
 signal z:std_logic_vector(15 downto 0);
 signal ci,co: std_logic;
 
begin
   FA:rca  port map(inp1,inp2,ci,z,co);			-- port map for RCA
       
   p0:process
       Variable inp1_rec: rnd_rec_t := (
            seed => (367, 23, 4, 221),   -- Change seed values to generate diff sequence
            bound_l => 432.0,
            bound_h => 2.0**12-1.0,  
            rnd => 0.0,
            trials => 25,
            p_success => 0.75,
            mean => 2.0,
            std_dev => 1.0
        );
		Variable inp2_rec: rnd_rec_t := (
            seed => (2079, 453, 221, 14),
            bound_l => 128.0,
            bound_h => 2.0**14-1.0,  
            rnd => 0.0,
            trials => 50,
            p_success => 0.8,
            mean => 2.0,
            std_dev => 1.0
        );
     variable inp1_int:integer;
    
	begin
        ci <= `0'; 
        for n in 0 to 15 loop
           uniform_d(inp1_rec);
           inp1_int:=integer(inp1_rec.rnd);
           inp1<=conv_std_logic_vector(inp1_int,16);
		   
		   uniform_d(inp2_rec);
           inp1_int:=integer(inp2_rec.rnd);
		   inp2 <= conv_std_logic_vector(inp1_int,16);
           
		   wait for 10 ns;   -- replace with appropriate delay value for 
                             -- carry propogation in 16 bit Ripple carry adder 
        end loop;  
	 wait;
  end process;

end architecture str;