Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use work.rnd2.all;

entity test_lab2 is
end entity test_lab2;

architecture str of test_lab2 is

component bcd_7seg is
   generic(gate_delay:Time:=4 ns);
   
   port(inp:in std_logic_vector(3 downto 0);
        z:out std_logic_vector(6 downto 0));
end component;


 constant number: natural:=8;
 signal inp1:std_logic_vector(3 downto 0);
 signal z:std_logic_vector(6 downto 0);
begin
 
   bcd1:  bcd_7seg port map(inp1, z);
          
	 p0:process
      variable inp1_rec: rnd_rec_t := (

            --seed => (0, 0, 0, 123),
            seed => (367, 23, 4, 191),
            --seed => (250, 1843, 3687, 991),
            -- bound_l => 1.0,
            bound_l => 0.0,
            -- bound_h => 2.0**4-1.0,  
            bound_h => 9.0,
            rnd => 0.0,
            trials => 10,
            p_success => 0.7,
            mean => 2.0,
            std_dev => 1.0
            -- the last 4 fields actually don't matter
         );
     variable inp_bcd:integer;
      begin
        for n in 0 to 15 loop
           uniform_d(inp1_rec);
           inp_bcd:=integer(inp1_rec.rnd);
           inp1<=conv_std_logic_vector(inp_bcd,4);
           wait for 5 ns; -- need to change the time to be 10-20% more
                          -- than your calculated max delay across all o/ps
        end loop;  
	 wait;
     end process;



end architecture str;