library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity tb_Booth_multiplier is
--
end entity tb_Booth_multiplier;

architecture test_Booth of tb_Booth_multiplier is

--change the path of file name as required  

file input_file : text open read_mode is "../input_booth_part1.txt"; 

--Include your Booth Multiplier component declaration here

signal ctrl_sig : bit_vector (14 downto 0);
signal clk : std_logic;

begin

--Instantiate your Booth multiplier and port map the various control signals 
--correctly here 

	clock_process: process is
	begin
	--generate a clock signal here with
	-- period = 1.1 * (delay of CLA/RCA + delay of D-ff), i.e., the 10 ns
	-- given below should be replaced by period/2 and the 20 ns by period 

		clk <= '0', '1' after 10 ns;
		wait for 20 ns;
	end process clock_process;
	
	-- This process reads the control signals from an input file 
	read_input: process is
	
        variable input_line: line;
	variable ch: character;
	variable v_ctrl_sig : bit_vector(14 downto 0);		
	begin

		while not endfile(input_file) loop
		
			readline(input_file, input_line); 
                	read(input_line, ch);

			--ignore if comments
			if ( ch /= '#') then 

				if ( ch = '1') then
					v_ctrl_sig(14) := '1';
				else
					v_ctrl_sig(14) := '0';
				end if;	

				read(input_line, v_ctrl_sig(13 downto 0)); 
				
				-- Generate random data here for loading reg Q if v_ctrl_sig(11) = '1' 
				-- and v_ctrl_sig(10) = '0'  
				-- Generate random data here for loading reg M if v_ctrl_sig(8) = '1' 
                		-- Generate random numbers in appropriate range to test overflow conditions. 
				-- Adding two large positive 
				-- numbers or two small negative numbers  produces an overflow
				
				wait until clk'event and clk = '1' and clk'last_value = '0';	
				ctrl_sig <= v_ctrl_sig;

			end if;	

		end loop;

		wait;

	end process;	

end architecture test_Booth;