Delay Model

To determine the accuracy of this delay model of unrouted circuits, we apply it on four benchmarks with known critically path delay after routing (from TD-Dragon benchmarks). Following is the result.

Circuit name	Mac32	Matrix	Vp2	Mac64
Our model delay	4.0	5.1	6.2	8.2
Routed delay	3.4	3.8	4.3	6.7

Our delays are generally only 22% larger and there is good fidelity between the two results.

The figure (a) on the left explains the WL model that we use. It is a star-graph model. The net length of a net n_j is:

Where x_i, y_i are the coordinates of pin u_i, x_c, y_c are the coordinates of the centroid of the pins of n_j, which are the average values of x and y coordinates of all pins.

The figure (b) illustrates how to calculate delay from driving pin u_d to sink pin u_i of a net with k pins. Since we don’t actually route the circuit, this is estimation of routed delay. Let R_d be the driving resistance, C_g the load capacitance of a sink pin, r (c) the unit wire resistance (capacitance), and

l_{d, i} the interconnect length connecting driver u_d to sink u_i

The delay consists of three part:

1. D₁( u_i, n_j)= Rd( c* L( n_j)+(k-1) C_g), which is the delay of driving resistance charging the whole interconnect capacitance and capacitance of load pins.

2. D₂( u_i, n_j)=rc*l²_{d, i+r}*l_{d, iCg} , which is the delay along the path from u_d to u_i

3. D₃( u_i, n_j)=r(l_{d, i}/2)((1-γ)(c* L( n_j)+(k-2)C_g)), referring to figure (b), part of the interconnect between u_d and u_i that lies on the main trunk (which assumes to be l_{d, i}/2) have to charge (1-γ) of the rest total capacitance C_total (besides load capacitance at u_i), which brings this part of delay.

The final delay is the sum of the above three part. γ is set to be 1/2 in our program.