| Description: Credit
4. Circuit technology, clocking, datapath design, controller design including
timing chains and microprogramming, memory systems design in caches, virtual
memory, multiple memory modules, I/O design including disk, serial and network
communications. Prerequisite:
ECE 267; and grade of C or better in ECE 265
Textbooks: Computer
Organization and Design, The Hardware/Software Interface, Patterson and
Hennessy, 2nd Ed., 1998.
Topics:
1. Technology overview
2. Datapath design and clocking
3. Control circuitry
4. Memory systems
a. main
memory
b. caches
c. virtual
memory
5. I/O
a. Disk
b. Controllers
c. Serial
communications
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Lab Topics:
Week 1 - Introduction to Modelsim Verilog simulator. Design SR Latch using structural description.
Week 2 - Design SR Latch using behavioral description.
Week 3 - Mux and Decoder using structure and behavioral descriptions.
Week 4 - Ripple Carry Adder in structural description.
Week 5 - Carry Lookahead Adder in structural description.
Week 6 - D Flip Flop.
Week 7 - 4 bit ALU.
Week 8,9 - Build Processor Components: register file, mux, control unit (FSM) in behavioral description.
Week 10,11,12 - Multi-cycle Implementation of a Processor Core using the components in lab8.
Week 13,14,15 - 5-Stage Pipelined Processor Core using the components in lab 8.
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