ECE 368---CAD Based Logic Design

Instructor: Prof. Shantanu Dutt

1. M/W/F 3-3:50pm, 316 DH.
   
   
2. Instructor's office hrs (930 SEO): M/W/F: 4:30-5:30 pm
   
   
3. TA: Li Li, email:lli29@uic.edu
   Office Hrs: TBA
   
   
4. Before the next lecture, remember to always go through the material covered in the previous lecture and make sure you understand it all. Ask Qs to TAs and me during office hours, and possibly in the next lecture.
   
   
5. Always do the given reading assignment for the class in which it will be needed. This way you'll get the most out of that lecture; otherwise you may not understand much of it. The reading assignments generally cover background material from pre-requisite courses or some nitty-gritty details like program syntax that are self explanatory.
   
   
6. Syllabus: pdf
   
   
7. A possible VHDL PC software along with an introductory VHDL tutorial: VHDL s/w and tutorial link
   
   
8. Other useful VHDL sources:
   
   (1) VHDL FAQs, etc.
   
   (2) On-line resources of the Ashenden textbook
   
   
9. Quartus Schematic Capture Based Simulation Tool: pdf
   
   
10. Lecture Notes (new addition/updation on 09/07)
    NOTE: The lecture notes cover many but not all topics. The rest of the topics will be covered from the text.
    
    
11. Lab instructions for setting up the Synopsys VHDL software and running it (for your lab assignments) (pdf).
    html instr (pdf is more recent version for instructions) + Source codes.
12. X Windows simulation tool (courtesy of Kevin Green)
    
    

1. The final exam will be on Wed May 7, 1:00 - 3:00 pm, in DH 316 (regular classroom).
   
   Final Exam Syllabus:
   1) Basics of behavioral, dataflow and structural VHDL descriptions.
   2) Timing issues: delays, simulation time, timing diagrams, signals vs. variables.
   3) Concepts in decomposing an architecture into multiple processes.
   4) FSM design and behavioral VHDL description.
   5) Generate statement -- especially use of generate statements to provide structural description of tree-like circuits (e.g. CLA, tree of AND gates).
   6) FSM Controller for datapaths.
   7) Sequential Multiplication and Division and proofs of correctness.
   8) Communication/Handshaking between modules.
   
   
2. Sample Finals: (1) pdf (2) pdf
   (3) pdf
   Note 1: The pipelining aspect in the pipelining + FSM controller problems in the 1st sample final (F'03)is not there in your final exam syllabus(but the FSM controller and module communication aspect is).
   Note 2: Also take a look at one of the sample midterm problems (see below) on controller FSM design and its solution.
   
   
3. Lab 7 -- due April 24: pdf .
   
   
4. The Synopsys Design Compiler introductory document prepared by Li Li is here (pdf) .
   The source files used in the example of this document is here (tarred and gzipped file) .
   Restore the above file using commands:
   "gunzip bcd4to7seg.tar.gz"
   "tar -xvf bcd4to7seg.tar"
   NOTE: After the above commands are executed, you will have the source VHDL files in a sub-dir. called "files"; so make sure you do NOT already have such a sub-directory where you have copied the bcd4to7seg.tar.gz file.
   
   
5. Lab 6 -- Part I: due April 10, Part II: due April 17: pdf .
   For Part I: Test bench and test control signals file
   
   
6. The midterm will be held on Fri Nov. 2
   
   Major Midterm topics:
   1) Basics of behavioral, dataflow and structural VHDL descriptions.
   2) Timing issues: delays, simulation time, timing diagrams, signals vs. variables.
   3) Concepts in decomposing an architecture into multiple processes.
   4) FSM design and behavioral VHDL description.
   5) Generate statements -- especially, the use of generate statements to provide structural description of tree-like circuits.
   
   
7. Sample Midterms: Qs & solutions:
   1) Fall 2006: pdf .
   2) Spring 2006: pdf .
   3) Fall 2005: pdf
   
   
8. Lab 5 -- due March 20 (end of lab): pdf .
   
   
9. Lab 4 -- (due March 6): pdf .
   
   
10. Lab 3 -- (part 1 due Feb. 14, part 2 due Feb. 21): pdf .
    TB for part 2 .
    
    
11. Lab 2 -- due Feb. 7 (end of lab): pdf .
    Test Bench for Lab 2: txt .
    Package"rnd2" used in the TB: txt .
    Copy this package (the file) to your "src" directory, and then compile it in the "sim" directory before compiling the TB. This is similar to first compiling the components of a structural (or mixed) arch. description before compiling the corresponding entity-architecture description that uses (i.e., instantiates) these components.
    
    
12. Lab 1 -- due Jan. 31 (beginning of lab). pdf .
    Codes for Lab 1: tarfile .
    Untar the tar file on a Unix machine using the command "tar -xvf lab1.tar".
    The files are also individually available at: file_dir with the following file names (append the file names to the above URL of the directory following the last '/' in the URL):
    dec2to4_behav_delay.vhdl, my_and_delay.vhdl, dec2to4_flow_delay.vhdl, my_not_delay.vhdl, dec2to4_struct_delay.vhdl, tb2-4.vhdl, dec3to8_mixed_delay.vhdl, tb3-8.vhdl, dec3to8_struct_delay.vhdl
    
    
13. Reading Assignment for week 2-3 from the reference text (can do from any logic design text; sections provided for the reference text---Digital Logic Circuit Analysis and Design, V.P. Nelson, et al., Prentice Hall, 1995.):
    1. Chapter 1 of text.
    2. Introduction to logic design: [0.1-0.2] from ref. text.
       
    3. Number Systems and Codes:} [1.1-1.2] from ref. text.
       
    4. Logic gates, synthesis of logic circuits using gates: [2.3-2.4.1, 2.5-2.6] from ref. text.