Shantanu Dutt

Bio

Vita and Research Highlights

Current Research Projects

New!

The FlowPlace Page

Contains timing-driven benchmarks and placement outputs produced by our FlowPlace TD incremental placer.

Journal and Refereed-Conference Publications

RA Positions

Teaching

• ECE 565---VLSI Design Automation (Fall 2007)
• ECE 368---CAD Based Logic Design (Spring 2008)
• ECE 366---Computer Architecture (Fall 2001)
• ECE 465---Digital Systems (Spring 2005)
• EECS 265---Intro. Logic Design (new name) (Spring 1998)
• EECS 566---Parallel Processing: Algorithms and Architectures (Spring 2006)

Education

• B.E. in Electronics and Communication Engineering, M.S. University of Baroda , Baroda, India, July 1983.
• M.Tech. in Computer Engineering, Department of Electrical and Communications Engineering, Indian Institute of Technology, Kharagpur , India, December 1984.
• Ph.D. in Computer Science and Engineering, Department of Electrical Engineering and Computer Science, University of Michigan , Ann Arbor, August 1990.
  Ph.D. thesis title: ``Designing and reconfiguring fault-tolerant multiprocessor systems''. Advisor: John P. Hayes .

Research Interests

Awards

• National Merit Scholarship, Govt. of India.
• University Scholarship from M.S. University of Baroda, Baroda, India, 1981.
• University Grant Commission Fellowship for the duration of M.Tech. studies,'83-'84.
• Rackham Predoctoral Fellowship, University of Michigan, May 1989 to April 1990.
• Research Initiation Award from NSF for the proposal ``Efficient Design of Fault-Tolerant Multiprocessors'' (Sept. 92 to Feb. 96)
• Twice selected among the top finalists (in 1991 and 1992) for the Engineering Research Initiation Grant.
• The paper ``Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures'', Proc. Eighteenth Fault Tolerant Comput. Symp. (FTCS), June 1988, Tokyo, pp. 328-333, coauthored with John P. Hayes, was selected as one of the most influential papers published over the last 25 years in FTCS. This paper has been published in a special Silver Jubilee volume, by the IEEE Computer Society Press.
• Best Paper award for the paper ``A probability-based approach to VLSI circuit partitioning'' (co-authored with W. Deng) at the Design Automation Conference, Las Vegas, June 1996.
• Invited paper "Tackling Roundoff Errors in Algorithm-Based Fault Tolerance" in Wiley Encyclopedia of Electrical and Electronics Engineering , Prof. John Webster, ed.

Invited Addresses and Colloquia

• ``Efficient design of fault-tolerant multicomputers'', Cray Research, Chippewa Falls, Wisconsin, July 1992.
• ``New anticipatory load balancing strategies for scalable parallel best-first search'', Workshop on Parallel Processing of Discrete Optimization Problems, DIMACS, Rutgers University, New Jersey, April 1994.
• ``A probabilistic approach to VLSI circuit partitioning'', Cadence Design Systems, San Jose, CA, June 1995.
• ``Node-covering, error-correcting codes and multiprocessors with very high average fault tolerance'', CRHC Seminar, University of Illinois, Urbana-Champaign, Illinois, Sept. 1995.
• ``New anticipatory load balancing strategies for scalable parallel best-first search'', EDRC Seminar, Carnegie-Mellon University, Pittsburgh, Sept. 1995.
• ``A probabilistic approach to VLSI circuit partitioning'', SRC CAD Center Seminar, Carnegie-Mellon University, Pittsburgh, Sept. 1995.
• ``Node-covering, error-correcting codes and multiprocessors with very high average fault tolerance'', ECE Seminar, University of Texas, Austin, Texas, Sept. 1995.
• ``Node-covering, error-correcting codes and multiprocessors with very high average fault tolerance'', CS Seminar, Texas A/&M University, College Station, Texas, Sept. 1995.
• ``New Algorithms for VLSI Circuit Partitioning and Placement for Area, Timing and Power Optimization'', Texas Instruments, Dallas, May 1996.
• ``New Algorithms for VLSI Circuit Partitioning and Placement for Area, Timing and Power Optimization'', IBM Rochester, July 1996.
• ``On-Chip Reconfiguration for Defect and Fault Tolerance of FPGAs'', Xilinx Corp., San Jose, CA, August 1996.
• ``A New Approach to Timing-Driven Partitioning and Placement with On-the-Fly Buffer Insertion'', Cadence Design Systems, Inc., San Jose, CA, Sept. 1996.

Funding

Most research projects are funded by NSF, DARPA, AFOSR and industry.

Graduate Students

• Fenghua Yuan , Ph.D. Thesis Topic: ``Incremental Placement and Floorplanning''.

Graduate Students

• Hasan Arslan , graduated Oct. 2004.
  Ph.D. Thesis: ``Incremental Routing Algorithms for FPGAs and VLSI Circuits''.
  Employment: Faculty member at Turkish university.
  
  
• Nihar R. Mahapatra, graduated, August 1996.
  Ph.D. Thesis: ``Highly Scalable Parallel Branch-&-Bound Algorithms for Solving Large Optimization Problems''.
  Employment: Associate Professor, Dept. of Electrical and Computer Engr., Michigan State University.
  
  
• Fran Hanchek , graduated, May 1997.
  Ph.D. Thesis: ``Design of Fault-Tolerant Arithmetic Circuits and FPGAs''.
  Employment: Senior Engineer at Intel Corp., Portland, Oregon,.

• Vishal Suthar , M.S. Thesis Topic: ``Logic and Interconnect Testing in Future Technology FPGAs with High Fault Densities''.
  
  
• Noha Mahmoud , M.S. Thesis Topic: ``Incremental Physical Design''.

• Franco Trovo , Dec. 2002, M.S. Thesis: ``Concurrent Control Flow Checking wit h Micro Rollback in a CISC Processor'', Dec. 2002.
  Currently volunteering for the Red Cross, Italy.
• Frederico Rota , Dec. 2002, M.S. Thesis: ``Control Flow Checking Using Main Memory Bus Monitoring in an Internal Cache Environment'', Dec. 2002.
  Employment: Internship in Japan.
• Vinay Verma , Sept. 2000, M.S. Thesis: ``Incremental Rerouting Algorithms for Field Programmable Gate Arrays'', Univ. of Illinois, Chicago.
  Employment: Xilinx, San Jose, California.
• Vimal Shanmugavel , 1998, M.S. Thesis: ``Low-Overhead Reconfiguration for Fault Tolerance in FPGAs'', Univ. of Illinois, Chicago. Employment: Tellabs, Chicago.
• Nihar Mahapatra , June 1993.
  M.S. Thesis: ``Scalable work distribution and duplicate pruning strategies for parallel A* algorithms''.
  Employment: See above.
• Mateen Malik Ahmed , Nov. 1994.
  M.S. Thesis: ``Design and simulation of a new multicomputer routing switch.''
  Employment: Motorola, Pakistan.
• Wenyong Deng , Oct. 1995.
  M.S. Thesis: ``New Algorithms for VLSI Circuit Partitioning''.
  Employment: Cadence Design Systems, San Jose, CA.
  
• Timothy Hartley , 1995
  M.S. Thesis: ``A test-bed for simulating reconfiguration in structurally fault-tolerant multicomputers.''
  Employment: AT Corp., Mnpls, MN.
• Nam Trinh , 1995.
  M.S. Thesis: ``Performance comparisons between k-ary n-cubes for divide-and-conquer parallel algorithms''.
  Employment: Anderson Consulting, Mnpls, MN.
  
• Scott Vanderlinde , graduated, March 1997.
  M.S. Thesis: ``Fault Tolerance for Optical Interconnects for Parallel Computers''.
  Emplyment: Guidant Systems, Mnpls, MN.
  
• Halim Theny, graduated, 1997. M.S. Thesis: ``New Algorithms for Partitioning and Placement of VLSI Circuits''.
  Employment: Intel Corp., Santa Clara, CA.

Professional Activities

• Co-Chair, TPC -- Tools and Methodology Track, ICCD 2004.
• Program Committee member of GLSVLSI, 2004.
• Session Chair at ICCD, 2003.
• Program Committee member of ICCD, 2003.
• Program Committee member of ICPP, 1998.
• NSF Panel Member 1997, 1999, 2002.
• Program Committee member of the Fault-Tolerant Computing Symp., 1997, 1998.
• Session Chair at the International Supercomputing Conf., May 1996.
• Session Chair at the Scalability Workshop at Int. Parallel Processing Symp., April 1993.
• Member of IEEE Computer Society, ACM, SIGARCH and SIGDA.
• Reviewed more than 100 papers for various journals and conferences, and more than 30 NSF proposals.